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Landauer in the last century has shown that information processing is intimately related to energy management [ 17 ].

From this perspective energy dissipation via heat production and energy transformation processes are two aspects of the same topic: energy management at the micro- and nanoscales. For our purposes, energy efficiency is defined as the percentage of energy input to a device consumed in useful work and not wasted as heat.

This definition, however, may not apply when we have to deal with processes taking place at the nanoscale see Chapter 2 of Vol. An ICT device is a machine that inputs information and energy under the form of work and processes both and outputs information and energy mostly under the form of heat. However, energy considerations become significant at the next stage that requires analyzing inputs and performing computational operations.

As mentioned earlier, the side effect of the advances in the computation process is the increasing heat production. Here the workhorse has been the field effect transistor FET , and in the last 40 years, the semiconductor industry has made impressive progresses in reducing the size of the CMOS components, thus increasing the computational density of microprocessors.

New types of scaling rules as well as new designs and materials were introduced to reduce the energy dissipation following the breakdown of the Dennard scaling rules where a number of fixed parameters in the transistor did not scale in a standard linear, quadratic or cubic way with the gate length of the transistor, e. While in principle, the switching energy of a metal—oxide—semiconductor field-effect transistor MOSFET could be reduced by reducing the supply voltage V DD indeed, this is what scaling over the last 40 years has been doing to reduce the energy and power dissipation , the finite bandgap of a semiconductor provides a lower limit below that the transistor will not switch on.

Moving to another semiconductor with a smaller bandgap than silicon allows some improvement to reduce energy, but apart from technological constraints the fundamental physics of the p-n junction for the contacts provides another limit for switching MOSFETs on and off. This is significantly smaller and faster than the FETs of today.

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FETs, however, have fundamental power and speed limits, and these cannot be overcome even by switching to new materials. The steep increase in CPU power density is mirrored by the increasing fraction of energy spent in cooling activities. Whereas there is still significant progress to be achieved by advanced CMOS, only by moving to a radically new technology can lower power dissipation potentially be achieved. Present low power CMOS is already at 3 aJ per operation excluding large fan-out and interconnect impedance and only predicted to reduce by a factor of 3 over the next 13 years.

The majority of improved future technologies do not produce any significant reduction in energy consumption per operation. Indeed a times the Landauer thermodynamic limit appears to be difficult to better when all the new proposed device technologies are considered. A number of new types of devices suggest that this barrier can be circumvented. More importantly, this switch demonstrates that the x Landauer limit can be broken. The intrinsic power dissipation per device switch versus delay time for CMOS and future devices as proposed in the ITRS future emerging technology roadmap [19, 20].

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The diagonal grey lines are lines of constant energy. The figure indicates a limit of about 1 aJ per switch for CMOS devices and zJ per device for the best proposed future switching device. Key device challenges can be summarized as: The cost of the lowest energy devices requires the latest CMOS technology node that now requires enormous economies of scale due to the cost of the foundries and technology.

The scaling of transistors to smaller dimensions is now not expected to decrease the switching energy significantly. If there is a change of the basic switching device to move to a significantly lower energy technology, then circuit architectures, design tools, verification, operating systems, and software may require rewriting or complete changes for basic operation or optimal performance.

Driving interconnects with multiple fan-out or an antenna have fundamental energy and noise limits that makes ultra-low energy consumption difficult. Significant opportunities can be divided into continued scaling of conventional transistor devices termed More Moore and adding new device concepts for computation termed beyond Moore or beyond CMOS or new functionality onto the base CMOS technology termed More than Moore.

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The key concept in More Moore is that the circuit architectures will be similar to present CMOS architectures and only the devices, voltages, or currents are changed. More Moore is looking at the challenges of scaling CMOS devices to dimensions below 10 nm, and a significant portion of this work is now investigating new channel materials and device architectures such as gate-all-around nanowires that will allow higher performance with lower voltages for reduced power operation.

The materials include Ge, III—Vs, semimetals, carbon-based materials, magnetic materials, and phase-change materials. Steep sub-threshold slope transistors allowing voltages for operation below the normal p-n junction limits are also being investigated. The major issue now being recognized by the semiconductor industry association and others is that scaling the transistor to smaller sizes may no longer result in lower energy devices; hence, More than Moore increased functionality is now a very diverse field of study: Devices with learning capability, e. Beyond Moore is the opportunity to completely change how information is processed.

This field is investigating the fundamental limits of information theory and if any of the known limits can be circumvented through innovative techniques. One example includes investigating if the Landauer limit requiring heat to be dissipated through the storage and erasure of information can be circumvented to allow zero energy switching. Spin wave devices are another example for a radical new technology that circumvents many of the limits of conventional transistor logic. Investigating methods of integrating device operation with energy harvesting has also been suggested where the heat dissipated and normally lost could be harvested to improve the overall thermodynamic system efficiency.

The Beyond Moore research area could have a large impact in reducing energy consumption of ICT devices but is also the most difficult to implement into systems as solutions may be radically different from conventional CMOS technology, architecture, and systems. The microarchitecture level considers the integration of many of the underlying fundamental device technologies. Transistor technologies and silicon processes are combined into useful blocks such as memory see, e. The scope for that integrated device is very broad, including ultralow power embedded devices, through general-purpose processors, up to high-performance network-on-chip components.

Based on current projections, a tenfold improvement in chip energy-efficiency is needed to maintain information technology IT energy scalability in the next decade. The ultimate limits from architecture designs are almost impossible to derive, but based on current technology, there is general agreement by academia and industry that new architectures are more promising to significantly reduce power consumption than improving the energy consumption of the basic switching device in the circuit.

The amount of energy consumption from a circuit architecture design for a given CMOS technology node is heavily dependent on how specific i. Applications specific integrated circuits ASICs designed for a single task can be optimized proving the lowest energy consumption, but such designs have no flexibility and cannot be reprogrammed. For microprocessors or microcontrollers that must be able to undertake a wide range of tasks, optimization to reduce energy consumption is significantly more difficult.

Microarchitecture exploits what is physically possible with contemporary technology and presents an interface through which other hardware and software can use the device. In hardware terms, this interface is, of course, physical and will typically obey a specified protocol. In software terms, the processing device presents a set of possible operations through an instruction set architecture ISA. If the ISA is a description of the behaviours of the device, then the microarchitecture is the implementation of those behaviours.

Advances in physics, transistor design, and device manufacturing techniques can benefit microelectronic devices of all kinds; however, microarchitecture design decisions are heavily influenced by the target market of the resultant product. While all devices strive to achieve good efficiency, balancing performance and power consumption, the application area will dictate design constraints such as size, the energy budget, and maximum power.

These are not necessarily strict boundaries and properties often transfer between areas over time, as technology or commercial pressures permit. Deeply embedded— An example of a deeply embedded device is the processor in a smart card. It must fit within a credit card form factor, cannot be modified once sent to the customer, be powered by a battery-backed device, and obey strict security protocols.

A new generation of deeply embedded devices is smart autonomous sensors, which due to their ability to seamlessly integrate with the environment have given rise to cyber-physical systems CPS and IoT platforms.

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This requires integration of heterogeneous components dedicated to signal acquisition e. The embedded system may also typically include wireless communication and run on batteries together with energy harvesters. Hence, one or more of the following constraints may apply: Physical size must be small, from millimetres to a few centimetres, depending on application.

The energy budget is finite as power may be intermittent or limited, often sub-watt or sub-milliwatt.

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Operating temperatures may vary significantly and the removal of excess heat quickly may not be possible. Predictable behaviour may be required to guarantee safety criteria or always-correct device functionality.

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All of the above points are relevant in an energy context. The energy consumption of the device dictates the temperature it runs at, the type of cooling required, how much processing and communication can be performed, and how long it will live. Predictable energy consumption is required to guarantee a particular battery life. To meet design goals within a small energy budget envelope, the design of each of the components is highly tailored to the targeted application see e. The microarchitectures of deeply embedded systems take various forms, but the following traits are common: They provide predictable execution times for many or all of the ISA instructions they support.

Their functional blocks, such as arithmetic and memory units, are often simpler than larger counterparts, to reduce power, improve predictability, and keep the device small.

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Their memory hierarchy is flat, avoiding caches that would impact predictability and increase device complexity. Programs may execute directly out of integrated flash storage, with RAM only used for read-write data. They feature compact instruction sets often 8- or bit instructions , with short execution pipelines and in-order execution. This means opportunities for performance enhancement are limited, but their implementation is simple.